Apparatus and method for diagnosing integrated circuit, and integrated circuit

ABSTRACT

An apparatus being able to not only detect a manufacturing defect of an integrated circuit but also specify a position at which the detect occurs even when outputs from scan paths are compressed and stored, or when the number of the scan paths is large. The apparatus has a pattern generator built in an integrated circuit to generate test patterns, a plurality of shift registers formed in parallel, into which the test patterns are shifted, and an output compressor for compressing a plurality of outputs shifted out from the shift registers with check bits of a Hamming code, and outputting them to the outside of the integrated circuit.

BACKGROUND OF THE INVENTION

[0001] 1) Field of the Invention

[0002] The present invention relates to an apparatus and a method formaking fault diagnosis to detect a manufacturing failure (fault) of anintegrated circuit such as an LSI (Large Scale Integration) or the likeand specify a position at which the fault occurs, and an integratedcircuit having a function of accomplishing the fault diagnosis.

[0003] 2) Description of the Related Art

[0004] Detection of a manufacturing failure of an integrated circuitsuch as an LSI is done by applying an appropriate signal value to aninput pin of the LSI using a tester (ATE; Automatic Test Equipment), andcomparing a signal value appearing at the output pin with an expectedresult. The signal value applied to the input pin and the expected valueto be appeared at the output pin are together called a test pattern.

[0005] Defect occurring inside an LSI due to a manufacturing failure ofthe LSI is called fault. To verify all faults that may occur inside theLSI, a large number of test patterns are required. A rate of the numberof faults that can be verified by a certain test pattern to the numberof all assumptive faults that are assumed inside an LSI is called faultcoverage, used as a scale when the quality of the test pattern ismeasured. When the LSI includes sequential circuit elements [flip-flop(F/F), latch and RAM (Random Access Memory)], complexity of creation oftest patterns is greatly increased.

[0006] In LSIs, scan design is general. In a scan-designed LSI, a shiftregister (called a scan path) is formed with sequential circuit elements(F/Fs, mainly) inside the LSI, a desired value is shifted into the shiftregister in a test, and a value of the shift register is read out aftera clock has been applied.

[0007] In such circuits, widely adopted is deterministic stored patterntest (hereinafter referred as DSPT). DSPT is made by storing testpatterns generated by an automatic test pattern generator (hereinafterreferred as an ATPG) in a tester (an ATE).

[0008]FIG. 6 is a diagram for illustrating a known scan design. FIG. 6shows a concept of the scan design as a block diagram. In ascan-designed LSI, there are formed a plurality of scan paths (shiftregisters) which are paths for testing the LSI, as shown in FIG. 6. Eachof the scan paths is formed with a plurality of F/Fs, each of which is amemory element. Test patterns are shifted into the scan paths from theirends (the left side in FIG. 6), and results of the test are outputtedfrom the other ends (the right side in FIG. 6). Incidentally, FIG. 6shows four scan paths, and each of the scan paths is formed by seriallyconnecting eight F/Fs.

[0009] The number of sequential circuit elements included inside an LSIis extremely increased with the integration of LSIs increased. Whensetting and reading are repetitively carried out for each test patternin all sequential circuit elements forming scan paths in the above DSPT,not only the test time increases but also a problem occurs that thememory capacity of the tester lacks due to an increase in quantity ofthe test data. Accordingly, execution of the test in DSPT becomesdifficult. Particularly, shortage of the memory capacity of the testercaused by an increase in quantity of test data largely raises the testcost because the memory has to be increased or the tester has to beupgraded.

[0010] To solve the above problem, the recent trend is built-in selftest (hereinafter referred as BIST). In BIST, patterns generated by apseudo-random pattern generator 2 are applied to an internal circuit(scan paths) of an LSI, and output results from the internal circuit areverified and stored by an output verifier 7, as shown in FIG. 7. As thepseudo-random pattern generator 2 and the output verifier 7, there areoften used linear feedback shift registers (hereinafter referred asLFSRs). Particularly, the output verifier 7 is called a multi-inputsignature register (hereinafter referred as MISR) since it compressesand stores output results as signatures. Incidentally, FIG. 7 is adiagram for illustrating a known BIST circuit FIG. 7 also shows eightscan paths between the pseudo-random pattern generator 2 and the outputverifier 7. Each of the scan paths is formed by serially connecting fourF/Fs.

[0011] The BIST circuit can generate a large number of test patternswithin a short time because the pseudo-random pattern generator ismounted inside the LSI, thus there is no need to store input testpatterns in an external tester. Results of the test are compressed andstored by the MISR, so that it is possible to greatly decrease thequantity of data to be loaded to the tester. Further, the BIST circuitcan increase the speed of the shifting-in/shifting-out operation to thescan paths by increasing the number of the scan paths, therebyshortening the test time.

[0012] Although the above problem with the DSPT can be improved byemploying BIST as above, there are still some problems.

[0013] Namely, a problem with BIST is the quality of the test (faultcoverage) because a pseudo-random pattern is used therein. To increasethe fault coverage, it is necessary to apply DSPT as an additional test,or insert a test point, which can improve the controllability andobservability, into the circuit inside the LSI.

[0014] In BIST, output data are compressed and stored in an MISR. Whenthe MISR captures an indeterminate value (X value) even once, allregisters in the MISR become the indeterminate state because of itsstructure, and values held in the registers are destroyed, which rendersthe test impossible.

[0015] Generally, sequential circuit elements including a RAM inside anLST are in the indeterminate state when the power supply is turned on.For this, it is necessary to beforehand apply a pattern to initializethese sequential circuit elements or take some measures in the circuitto prevent propagation of the indeterminate state to the MISR.Additionally, it is necessary to prevent occurrence of conflict or thefloating state of the bus caused by a random pattern when the bus isdesigned, for example. These severe constraints in design are placed onthe designer when the BIST is applied to a practical circuit. Further,there is another problem that area overhead of the circuit orperformance degradation occurs because of an additional circuit for BISTand insertion of a test point.

[0016] Inventors of this application have proposed a technique disclosedin Japanese Patent Application No. 2000-372231, which can solve theabove problems with DSPT and BIST, shorten the test time, decrease thedata quantity, and accomplish a high-quality test (test having a highfault coverage). FIG. 8 (block diagram) shows a structure of a testcircuit applied this technique.

[0017] A test circuit shown in FIG. 8 is based on a BIST circuit similarto that shown in FIG. 7 on an LSI, and a pattern modifier 4 and a mask 5are added to the BIST circuit. Patterns generated by the pseudo-randompattern generator (LFSR) 2 are modified into patterns equivalent to onesgenerated by the ATPG, and shifted into the scan paths. After a testclock is applied, outputs from the scan paths are compressed by andstored in the MISR in the output verifier 7 through the mask 5. At thistime, an indeterminate value (X value) in the outputs is masked by themask 5. Incidentally, eight scan paths are shown between the patternmodifier 4 and the mask 5, and each of the scan paths is formed byserially connecting four F/Fs in FIG. 8.

[0018] When patterns generated by an ATPG are shifted into scan pathsand a test is made, the number of F/Fs to which values (1 or 0)explicitly set on the basis of the patterns is extremely small (severalpercent) among all F/Fs. In the test circuit shown in FIG. 8, onlyvalues to be explicitly set to F/Fs as above are given to the patternmodifier 4 using a control signal from an external tester, andpseudo-random patterns from the pseudo-random pattern generator 2 aremodified by the pattern modifier 4 into high-quality patterns equivalentto ones generated by the ATPG. An interminate value is prevented frombeing captured into the MISR by the mask 5, whereby the designer can dodesigning in a way to readily and certainly satisfy one of designconstrains in BIST, which can largely reduce the burden on the designer.

[0019] The LSI testing method of compressing output results and storingthem in the MISR as is made in the BIST circuit shown in FIG. 7 or thetest circuit shown in FIG. 8 is aimed mainly to judge the quality of anLSI under test. In practical LSI manufacturing, it sometimes becomesnecessary to examine a cause of a failure in an LSI that has been judgedto have the failure in order to solve a problem in the LSI manufacturingprocess or improve the yield rate. In such case, it is necessary tospecify where the defect exists inside the LSI.

[0020] Generally, specifying a position of a fault on the basis of atest pattern given by a tester and information on a portion where anobserved value of the tester disagrees with an expected value is calledfault diagnosis. Since it is possible to observe outputs of each patternin DSPT, the fault diagnosis is relatively easy. A fault that can bedetected by each pattern and a position (F/F) at which the fault isdetected can be known in fault simulation, so that a candidate fault canbe narrowed down on the basis of the disagreement information of thetester.

[0021] On the contrary, the BIST circuit shown in FIG. 7 or the testcircuit shown in FIG. 8 compresses output results and stores them in theMISR of the output verifier 7, and reads out values in the MISR afterthe test is completed, so that the fault diagnosis is difficult. Namely,even if presence of a fault can be detected, it is impossible to specifya position of the fault because the output results are compressed.Additionally, the number of scan paths is increased to increase thespeed of the test in the test such as BIST or the like, so that outputsof all scan paths cannot be observed at external pins because oflimitation of the number of pins of an LSI. In other words, the faultdiagnosis is impossible.

SUMMARY OF THE INVENTION

[0022] In the light of the above problems, an object of the presentinvention is to provide a technique, which can not only detect amanufacturing failure (fault) of an integrated circuit but also specifya position at which the failure occurs even when outputs from scan pathsare compressed and stored, or the number of scan paths is large.

[0023] The present invention therefore provides a diagnosing apparatusfor an integrated circuit comprising a pattern generator built in anintegrated circuit to generate test patterns, a plurality of shiftregisters formed in parallel with sequential circuit elements inside theintegrated circuit, the test patterns generated by the pattern generatorbeing shifted into the shift registers, respectively, and an outputcompressor for compressing a plurality of outputs shifted out from theshift registers with check bits of a Hamming code, and outputting thecompressed outputs as a compressed value to the outside of theintegrated circuit.

[0024] The diagnosing apparatus may further comprise diagnosing meansfor comparing an output expected value beforehand obtained with thecompressed value from the output compressor to make fault diagnosis.When the diagnosing means diagnoses as a result of the comparison that afault occurs at one position, the diagnosing means may specify a shiftregister in which the fault exists.

[0025] The present invention further provides a diagnosing method for anintegrated circuit comprising the steps of generating test patterns by apattern generator built in an integrated circuit, shifting the testpatterns generated by the pattern generator into a plurality of shiftregisters formed in parallel with sequential circuit elements inside theintegrated circuit, compressing a plurality of outputs shifted out fromthe plural shift registers with check bits of a Hamming code, andoutputting the compressed outputs as a compressed value to the outsideof the integrated circuit, and comparing an output expected valuebeforehand obtained with the compressed value from the integratedcircuit to make fault diagnosis.

[0026] The present invention still further provides an integratedcircuit, in which the above pattern generator, a plurality of the shiftregisters and the output compressor are built.

[0027] The present invention still further provides a diagnosingapparatus for an integrated circuit comprising a pattern generator, aplurality of shift registers both similar to those described above,along with at least one EOR (exclusive OR) tree circuit for compressinga plurality of outputs shifted out from the shift registers, andoutputting the compressed outputs as a compressed value to the outsideof the integrated circuit, and a control circuit for enabling one of theplurality of outputs to be inputted to the EOR tree circuit.

[0028] The above diagnosing apparatus may further comprise a diagnosingmeans for comparing an output expected value beforehand obtained withthe compressed value from the EOR tree circuit to make fault diagnosis.The control circuit may enable the plurality of outputs one by one, theEOR tree circuit may compress outputs enabled by the control circuit,and successively output the compressed outputs as the compressed valueto the outside of the integrated circuit, and the diagnosing means maymake the fault diagnosis on the shift registers one by one on the basisof the compressed value from the EOR tree circuit to specify a shiftregister in which the fault exists.

[0029] The present invention still further provides a diagnosing methodfor an integrated circuit comprising the steps of generating testpatterns by a pattern generator built in an integrated circuit, shiftingthe test patterns generated by the pattern generator into a plurality ofshift registers formed in parallel with sequential circuit elementsinside the integrated circuit, enabling a plurality of outputs shiftedout from the shift registers one by one, compressing the enabled outputsby an EOR (exclusive OR) tree circuit, and successively outputting thecompressed outputs as a compressed value to the outside of theintegrated circuit, and comparing an output expected value beforehandobtained with the compressed value from the EOR tree circuit to makefault diagnosis.

[0030] The present invention still further provides an integratedcircuit, in which a pattern generator, shift registers, an EOR(exclusive OR) tree circuit and a control circuit similar to thosedescribed above are built.

[0031] According to the diagnosing apparatus and method for anintegrated circuit and the integrated circuit of this invention, aplurality of outputs shifted out from a plurality of shift registers arecompressed with check bits of a Hamming code, and outputted to theoutside. Therefore, it is possible to observe information on a number ofscan paths at a small number of external output pins, and accomplishdiagnosis on an LSI under test such as BIST or the like with smallcircuit overhead. Although it is necessary to compare an expected valueby a tester for each test pattern when diagnosis is made, diagnosis at ahigher speed then DSPT becomes possible because information on a numberof scan paths is compressed and encoded. Even when outputs from the scanpaths are compressed and stored, or even when the number of the scanpaths is large, it is possible to not only detect a manufacturingfailure (fault) of an integrated-circuit but also specify a position atwhich the failure occurs.

[0032] Since a plurality of outputs shifted out from a plurality ofshift registers are enabled one by one, and the enabled outputs arecompressed by the EOR (exclusive OR) tree circuit and successivelyoutputted to the outside, it is possible to accurately specify all scanpaths in which faults exist when fault diagnosis is made on an LSI undertest such as BIST OR the like. Even when a number of faults concurrentlyexist because a new manufacturing process is started, accurate, certainfault diagnosis is possible.

[0033] At this time, outputs from shift registers corresponding topatterns of pattern numbers in a predetermined range generated by thepattern generator are enabled, and the fault diagnosis is made. Whereby,it is possible to narrow down a pattern number where a fault occurs tospecify a position of the fault in the scan path.

[0034] Test patterns generated by the pattern generator are modified bythe pattern modifier and inputted to a plurality of shift registers(scan path). It is thereby possible to increase the number of the scanpaths to decrease the number of the stages of the scan paths, thuslargely shorten the test time for the integrated circuit. It is alsopossible to solve the problems with DSPT and BIST, and generate testpatterns which provide advantages of the both and enable a high-qualitytest within a short time. At this time, only meaningful data(information on F/Fs required to be set values) is supplied from thetester (external input) and modified, which allows a large decrease inquality of the data to be stored in the tester. Therefore, ahigh-quality test becomes possible without imposing server design ruleson the designer and without an expensive tester.

[0035] An indeterminate value in outputs from a plurality of shiftregisters formed with sequential circuit elements inside the integratedcircuit is masked, and a masked output result is verified by the outputverifier. It is thereby possible to prevent the compressed result frombeing ruined by the indeterminate state even if the output results fromthe sequential circuit elements are compressed and read out to theoutside.

BRIEF DESCRIPTION OF THE DRAWINGS

[0036]FIG. 1 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to a first embodiment ofthis invention;

[0037]FIG. 2 is a diagram for illustrating a compressing method (anexample of error correction using a Hamming code) with check bits of aHamming code according to the first embodiment;

[0038]FIG. 3 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to a second embodiment ofthis invention;

[0039]FIG. 4 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to a third embodiment ofthis invention;

[0040]FIG. 5 is a time chart for illustrating an operation according tothe third embodiment;

[0041]FIG. 6 is a diagram for illustrating a known scan design (DSPT);

[0042]FIG. 7 is a diagram for illustrating a known BIST circuit; and

[0043]FIG. 8 is a block diagram showing a structure of a test circuitfor an integrated circuit with a pattern modifier and a mask.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0044] Hereinafter, description will be made of embodiments of thisinvention with reference to the drawings.

[0045] [1] Description of First Embodiment

[0046] For fault diagnosis, agreement/disagreement information(information on whether a scan path output agrees with an expected valuefor each test pattern) for each test pattern is necessary, like DSPT.Since a scan path output is not compared with an expected value for eachtest pattern in BIST, it is necessary to read values of F/Fs for eachtest pattern to the outside. However, the number of inside parallel scanpaths is increased for the purpose of a high-speed test in BIST, so thatexternal output pins in number equal to all scan paths cannot beprepared because of limitation of the number of input/output pins of anLSI. Accordingly, some measures are necessary to compress information ofa number of scan paths and observe it at a small number of externaloutput pins. A first embodiment of this invention provides suchmeasures.

[0047]FIG. 1 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to the first embodiment ofthis invention. The diagnosing apparatus according to the firstembodiment comprises a pseudo-random pattern generator (patterngenerator, LFSR) 2, a plurality of scan paths, an output verifier (MISR)7, and an output compressor 10, as shown in FIG. 1. The diagnosingapparatus is built in an LSI 1A that is an integrated circuit to betested.

[0048] The LSI 1A includes a plurality of F/Fs (sequential circuitelements). In the LSI 1A, a plurality of scan paths (shift registers)are formed in parallel with the F/Fs. In the example shown in FIG. 1,eight scan paths are formed in parallel, and each of the scan paths isformed by serially connecting four F/Fs.

[0049] In the diagnosing apparatus according to the first embodiment,patterns generated by the pseudo-random pattern generator 2 are shiftedinto the scan paths, and output results of the scan paths are compressedand stored by the output verifier 7. The output verifier 7 is formedwith a plurality of exclusive OR (EOR) circuits and a plurality ofregisters. The output verifier 7 compresses (encodes) output resultsfrom the scan paths as signatures and stores them, then finally outputsthe output results for predetermined test patterns as a value encodedinto eight bits.

[0050] The output compressor 10 is formed with exclusive OR circuits(EOR circuits) 11 through 21, as shown in FIG. 1. The output compressor10 compresses a plurality of outputs (8-bit data in FIG. 1) shifted outfrom the plural scan paths using check bits (four bits in FIG. 1) of aHamming code. Namely, the output compressor 10 corresponds to check bitsof a Hamming code, formed with the EOR circuits 11 through 21 realizingcheck bits of a Hamming code. Hamming code is a family of errorcorrection codes, which can correct an error of one bit. By adding checkbits to actual information bits, error correction can be done in aHamming code. When the information bits are four bits (x1,x2,x3,x4), thecheck bits require three bits (y1,y2,y3). FIG. 2 shows an example oferror correction in this case. FIG. 2 is a diagram for illustrating acompressing method (an example of error correction using a Hamming code)using check bits of a Hamming code according to the first embodiment ofthis invention.

[0051] In the example shown in FIG. 2, the information bits are fourbits (x1,x2,x3,x4) and the check bits are three bits (y1,y2,y3), asdescribed above. The check bits (y1,y2,y3) are calculated from theinformation bits (x1,x2,x3,x4) on the basis of an expression shown inFIG. 2. In this case, a syndrome is of three bits (z1, z2, z3), and anerror vector corresponding to the syndrome is beforehand given as shownin FIG. 2.

[0052] If the original data is (0,1,0,0) at this time, (1,0,1) should beobtained as the check bits. Namely, when (0,1,0,0) are expected as scanpath outputs for certain test patterns, (1,0,1) should be outputted ascheck bit outputs from the output compressor 10, so that (1,0,1) arebeforehand obtained as an output expected value.

[0053] Assuming that when (0,1,0,0) are expected as scan path outputs,an error happens therein due to a fault, x3 becomes, for example, “1”,and (0,1,1,0) are obtained as the scan path outputs. In this case,(0,1,1) are obtained as the check bits (outputs of the output compressor10), an exclusive OR (EOR) is calculated from the check bits (0,1,1) andthe output expected value (1,0,1), whereby a syndrome (1,1,0) isobtained.

[0054] An error vector (x1,x2,x3,x4,y1,y2,y3) corresponding to theobtained syndrome (1,1,0) is (0,0,1,0,0,0,0) as shown in FIG. 2. In aHamming code, an exclusive OR of (x1,x2,x3,x4) of the error vector andthe scan path outputs (0,1,1,0) is calculated, whereby original data canbe restored.

[0055] According to the first embodiment, there is no need to restorethe original data. When the syndrome is calculated, a bit of the errormixing therein, that is, a scan path in which a fault exists, isspecified.

[0056] In the example shown in FIG. 1, the information bits are eightbits (x1,x2, . . . ,x8). In this case, the method described above withreference to FIG. 2 is expanded and applied since the check bits becomesfour bits (y1,y2,y3,y4). Namely, scan path outputs (x1,x2, . . . ,x8) ofeight bits are compressed into check bit data (y1,y2,y3,y4) of four bitsof a Hamming code of four bits by the output compressor 10 (EOR circuits11 through 21), and outputted to the outside of the LSI 1A.

[0057] According to the first embodiment, there is provided a tester(diagnosing means) not shown, to which outputs [check bit data(y1,y2,y3,y4)] from the output compressor 10 are inputted. The testerbeforehand holds therein check bit data to be obtained when no fault(error) occurs as an output expected value. The tester compares theoutput expected value with outputs (check bit data) from the outputcompressor 10, and makes fault diagnosis.

[0058] In concrete, an exclusive OR is calculated from the outputexpected value and the check bit data from the output compressor 10 toobtain a syndrome, and a fault position is determined on the basis ofthe syndrome, as described above. When no fault exists, the outputexpected value agrees with the check bit data from the output compressor10, and each bit of the syndrome becomes “0”. When a fault exists in oneof a plurality of the scan paths, the output expected value disagreeswith the check bit data from the output compressor 10, and an error ofone bit in scan path outputs (x1,x2, . . . ,x8) of eight bits can bespecified on the basis of an error vector corresponding to the obtainedsyndrome. Namely, it is possible to specify one scan path where thefault occurs (fault position).

[0059] When faults concurrently occur in two or three scan paths, aresult of outputs of the output compressor 10 disagrees with an expectedvalue of the tester, as does when a fault occurs in one scan path.However, it is not always that the fault occurs in a scan path obtainedwith the syndrome, thus it is impossible to specify the fault position(a scan path in which the fault exists). In this case, it is onlypossible to indicate presence of the fault. When faults concurrentlyoccur at not less than four positions, there is a case where a result ofoutputs of the output compressor 10 agrees with an expected value of thetester even though the faults exist, thus presence/absence of a faultcannot be sometimes accurately indicated.

[0060] According to the first embodiment of this invention, a pluralityof outputs shifted out from a plurality of scan paths are compressed andencoded into check bits of a Hamming code, then outputted to the outsideof the LSI 1A. It is thereby possible to observe information on a numberof scan paths at a small number of external output pins (four in theexample in FIG. 1). Accordingly, diagnosis of the LSI 1A under test suchas BIST or the like can be made with small circuit overhead.

[0061] In fault diagnosis, it is necessary to compare expected values bya tester for each test pattern. However, information on a number of scanpaths is compressed and encoded, so that diagnosis higher than DSPTbecomes possible. Even when outputs from scan paths are compressed andstored, or even when the number of scan paths is large, it is possibleto not only detect a manufacturing defect (fault) of the LSI 1A but alsospecify a position of a fault (scan path) if the fault occurs at oneposition. According to the first embodiment, when faults occur in two orthree scan paths, only presence of the faults is indicated. However,even only indicating presence of faults is considered to be greatlyeffective to the LSI 1A in the mass production stage.

[0062] As shown by chain double-dashed line in FIG. 1, a patternmodifier 4 which modifies test patterns generated by the pseudo-randompattern generator 2 according to an external input and inputs them intothe plural scan paths (shift registers), and a mask 5 which masks anindeterminate value (X value) in outputs of the plural scan paths andoutputs them to the output verifier 7, then to the output compressor 10may be also built in the LSI 1A, like the testing apparatus describedabove with reference to FIG. 8.

[0063] At this time, test patterns generated by the pseudo-randompattern generator 2 are inputted to the pattern modifier 4. A controlsignal from the tester (not shown) is inputted to the pattern modifier 4through a control input pin or the like. The pattern modifier 4 modifiesonly values of F/Fs in which values thereof are required to be setaccording to the control signal, and inputs and sets the values to theleading F/Fs of relevant scan paths.

[0064] The mask 5 masks an indeterminate value (X value) among values ofthe last F/Fs of the scan paths according to the control signal inputtedthrough the control input pin or the like to convert the indeterminatestate to the determinate state, then inputs values of the last F/Fs ofthe scan paths to the output verifier 7 and the output compressor 10.

[0065] By modifying test patterns generated by the pseudo-random patterngenerator 2 by the pattern modifier 4 and inputting them into aplurality of scan paths, it becomes possible to increase the number ofthe scan paths to decrease the number of stages of the scan paths (thenumber of F/Fs in each scan path), thereby decreasing the test time forthe LSI 1A.

[0066] Additionally, it is also possible to solve the problems with DSPTand BIST, and generate test patterns within a short time which haveadvantages of the both and enable a high-quality test. At that time,only meaningful data (information on an F/F to which a value is requiredto be set) is supplied from the tester (external input) and modified, sothat the quantity of data to be stored in the tester can be largelydecreased. Accordingly, a high-quality test becomes possible withoutimposing severe design rules on the designer and without an expensivetester.

[0067] Further, the mask 5 masks an indeterminate value (X value) inoutputs from the plural scan paths formed with F/Fs inside the LSI 1A,and the output verifier 7 verifies the masked output results, whereby aresult of compression is not ruined by the indeterminate value even ifthe output results from the F/Fs are compressed and read out to theoutside.

[0068] [2] Description of Second Embodiment

[0069] When a plurality of faults concurrently occur, it is impossibleto specify positions of the faults in the above first embodiment. Thiseasily occurs when a new manufacturing process is started, thusnecessity of fault diagnosis is large. According to second and thirdembodiments, it becomes possible to accurately specify all scan paths inwhich faults occur as necessary.

[0070]FIG. 3 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to the second embodimentof this invention. As shown in FIG. 3, the diagnosing apparatusaccording to the second embodiment comprises a pseudo-random patterngenerator 2, a plurality of scan paths, and an output verifier 7 similarto those according to the first embodiment, along with an outputselector 30 instead of the output compressor 10. The diagnosingapparatus is built in an LSI 1B that is an integrated circuit to betested.

[0071] Like the LSI 1A according to the first embodiment, the LSI 1Bincludes a plurality of F/Fs (sequential circuit elements). In the LSI1B, these F/Fs form a plurality of scan paths (shift registers) inparallel. In an example shown in FIG. 3, eight scan paths are formed inparallel, and each of the scan paths is formed by serially connectingfour F/Fs.

[0072] In the diagnosing apparatus according to the second embodiment,patterns generated by the pseudo-random pattern generator 2 are shiftedinto the scan paths, and output results from the scan paths arecompressed and stored by the output verifier 7, as well. The outputverifier 7 is formed with a plurality of EOR circuits and a plurality ofregisters. The output verifier 7 compresses (encodes) output resultsfrom the scan paths and stores them, and finally outputs the outputresults for predetermined test patterns as an eight-bit encoded value.

[0073] The output selector 30 comprises two EOR (exclusive OR) treecircuits 31 and 32, and a control circuit 40, as shown in FIG. 3.

[0074] The EOR tree circuit 31 is formed with three exclusive ORcircuits (EOR circuits) 33, 34 and 35, which compresses outputs shiftedout from upper four scan paths shown in FIG. 3, and outputs them to theoutside of the LSI 1B. Similarly, the EOR tree circuit 32 is formed withthree exclusive OR circuits (EOR circuits) 36, 37 and 38, whichcompresses outputs shifted out from lower four scan paths shown in FIG.3, and outputs them to the outside of the LSI 1B. The control circuit 40comprises a decoder 41, and eight OR circuits (logical sum circuits) 42through 49. The control circuit 40 enables one of plural outputs (fouroutputs, here) to be inputted to each of the EOR tree circuits 31 and32.

[0075] The OR circuits 42 and 43 input logical sums of outputs of thefirst and second scan paths from the top shown in FIG. 3 and selectionsignals from the decoder 41 to two input terminals of the EOR circuit33, respectively. Similarly, the OR circuits 44 and 45 input logicalsums of outputs of the third and fourth scan paths from the top shown inFIG. 3 and selection signals from the decoder 41 to two input terminalsof the EOR circuit 34, respectively. The OR circuits 46 and 47 inputlogical sums of outputs of the fifth and sixth scan paths from the topshown in FIG. 3 and selection signals from the decoder 41 to two inputterminals of the EOR circuit 36, respectively. The OR circuits 48 and 49input logical sums of outputs of the seventh and eighths scan paths fromthe top shown in FIG. 3 and selection signals from the decoder 41 to twoinput terminals of the EOR circuit 37, respectively.

[0076] The decoder 41 gives selection signals to the OR circuits 42through 49 according to a control signal fed from the outside of the LSI1B in order to input only outputs of scan paths to be enabled to the EORtree circuits 31 and 32.

[0077] According to the second embodiment, the decoder 41 switches onlyone of selection signals to be inputted to the upper four OR circuits 42through 45 from “1” to “0” and switches only one of selection signals tobe inputted to the lower four OR circuits 46 through 49 from “1” to “0”according to the control signal from outside of LSI 1B, in order toenable only one of outputs of the upper four scan paths to be inputtedto the EOR tree circuit 31 and to enable only one of outputs of thelower four scan paths to be inputted to the EOR tree circuit 32. The ORcircuits 42, 43, 44 or 45, and 46, 47, 48 or 49 inputted selectionsignals “0” from the decoder 41 allow outputs of scan paths inputted tothese OR circuits to pass therethrough, and input outputs of these scanpaths to the EOR tree circuits 31 and 32. Outputs of the OR circuits 42through 49 to which selection signals “1” have been inputted alwaysbecome “1”, so that outputs of the relevant scan paths cannot passthrough these OR circuits.

[0078] According to the second embodiment, two outputs among outputs ofthe eight scan paths are selected and enabled, and outputted to theoutside of the LSI 1B from two external output pins through the EOR treecircuits 31 and 32 in one test. Namely, when the test is repeated fourtimes, the test on all eight scan paths can be completed.

[0079] According to the second embodiment, a tester (diagnosing means)not shown is provided, to which outputs from the output selector 30 areinputted. Output expected values that should be obtained when no fault(error) occurs are beforehand stored in the tester, and compares theexpected values with outputs from the output selector 30 to make faultdiagnosis.

[0080] In the second embodiment, when diagnosis is made on the LSI 1B towhich a test such as BIST or the like has been applied, the controlcircuit 40 enables outputs of scan paths to be inputted to the EOR treecircuits 31 and 32 one by one with or without concurrent faults, withthe above structure. Each of the EOR tree circuits 31 and 32 compressesoutputs that have been enabled by the control circuit 40, andsuccessively outputs them to the outside of the LSI 1B. The above testercompares an expected value with outputs from the EOR tree circuits 31and 32 to make fault diagnosis, and specifies a scan path whose outputdoes not agree with the output expected value as a scan path in which afault occurs.

[0081] The above process is repeated plural times (four times in the LSI1B according to the second embodiment shown in FIG. 3) to diagnose allscan paths, thereby to specify positions of all faults (scan paths inwhich the faults exist). In more detail, in the first test, theselection signals of the decoder 41 are so set as to enable only thefirst scan paths connected to the EOR tree circuits 31 and 32, and atest is made on the first scan paths. A scan path in which a faultexists is specified on the basis of disagreement information of thetester for each test pattern.

[0082] At this time, a group to which that scan path belongs (a group ofthe EOR tree circuit 31 or a group of the EOR tree circuit 32) isspecified on the basis of disagreement information from either one oftwo external output pins provided correspondingly to the EOR treecircuits 31 and 32. Further, since it is recognized that the first scanpath in each group is enabled by the selection signal from the decoder41, a scan path in which a fault exists can be specified.

[0083] Similar test is repeated n times (n=4 in the second embodiment)to test up to the n-th scan path connected to each of the EOR treecircuits 31 and 32, so that all scan paths in each of which a faultexists can be specified.

[0084] It should be noted that it is necessary to recalculate the outputexpected values used in the test carried out n times according to asetting of the mask for diagnosis.

[0085] According to the second embodiment, outputs to be inputted toeach of the EOR tree circuit 31 and 32 from the plural scan paths areenabled one by one by the control circuit 40, and the enabled outputsare compressed by each of the EOR tree circuit 31 and 32, andsuccessively outputted to the outside of the LSI 1B. It is therebypossible to accurately specify all scan paths in which faults exist whenfault diagnosis is made on an LSI under test such as BIST or the like.Accordingly, even if a plurality of faults concurrently exist because anew manufacturing process is started, accurate, certain fault diagnosisis possible.

[0086] [3] Description of Third Embodiment

[0087]FIG. 4 is a block diagram showing a structure of a diagnosingapparatus for an integrated circuit according to a third embodiment ofthis invention. As shown in FIG. 4, the diagnosing apparatus accordingto the third embodiment comprises a pseudo-random pattern generator(LFSR) 2, a plurality of scan paths (shift registers) and an outputverifier (MISR) 7 similar to those according to the first or secondembodiment, along with a pattern modifier 4 similar to that according tothe first embodiment between the pseudo-random pattern generator 2 andthe plural scan paths, and a mask 5 similar to that according to thefirst embodiment between the plural scan paths and the output verifier7. The diagnosing apparatus is built in an LSI 1C that is an integratedcircuit to be tested.

[0088] Like the LSI 1A according to the first embodiment, the LSI 1Cincludes a plurality of F/Fs (sequential circuit elements). In the LSI1C, the F/Fs form a plurality of scan paths (shift registers) inparallel. In the example shown in FIG. 4, eight scan paths are formed inparallel, and each of the scan paths is formed by serially connectingfour F/Fs.

[0089] In the diagnosing apparatus according to the third embodiment,test patterns generated by the pseudo-random pattern generator 2 areinputted to the pattern modifier 4. A control signal is inputted to thepattern modifier 4 from a tester (not shown) through a control input pinor the like. The pattern modifier 4 modifies only values for F/Fs towhich the values are required to be set, and inputs and sets the valuesto the leading F/Fs of the scan paths.

[0090] The test patterns modified as above are shifted into the scanpaths, and output results from the scan paths are inputted to the mask5. The mask 5 masks an indeterminate value (X value) among values of thelast F/Fs of the scan paths according to a control signal inputted fromthe control input pin or the like to convert the indeterminate state tothe determinate state. Then, the values of the last F/Fs of the scanpaths are inputted to the output verifier 7, and compressed by theoutput verifier 7 and stored therein. The output verifier 7 is formedwith a plurality of EOR circuits and a plurality of registers, asdescribed above. The output verifier 7 compresses (encodes) outputresults from the scan paths as signatures and stores them therein, thenfinally outputs them as a value encoded into eight bits.

[0091] The mask 5 is provided with a decoder 51, logical sum circuits(OR circuits) 52, 53 and 54, logical product circuits (AND circuits) 55and flip-flops (F/Fs) 62 in order to mask an indeterminate value (Xvalue) in outputs of the plural scan paths. To the mask 5 inputted arecontrol signals through eight control input pins (b1 through b8), andoutputs from the last F/Fs of eight scan paths #0 through #7.

[0092] The mask 5 controls a shift clock to the output verifier (and thepseudo-random pattern generator 2) and a shift clock to the F/Fs on thescan paths. When masking the indeterminate state, the shift clock to theF/Fs on the scan paths and the output verifier 7 (and the pseudo-randompattern generator 2) is suppressed, but only the shift clock to F/Fs 62in the following stage of the last F/Fs on the scan paths is applied.Each of the F/Fs 62 holds an inversion state independently of the lastF/F on the scan path. Such structure slightly increases overhead of thecircuit, but makes it possible to separate the output verifier 7 fromthe scan paths #0 through #7 and easily modularlizes them, which allowsre-ordering process of optimally changing the order of the scan F/Fs atthe time of layout in which physical placement and routing areperformed.

[0093] The mask 5 enables a masking operation with the most significantbit (b1) of a control input, and has a decoder 51 to which the lowerseven bits (b2 through b8) of the control input are inputted. Accordingto a result of decoding by the decoder circuit 51, the OR circuit 52converts an indeterminate value (X value) inputted from a specific oneof the eight scan paths to a “1” state value (or a “0” state value)whereby the indeterminate value is masked.

[0094] When “1” is inputted to the control input pin b1, the output ofthe OR circuit 53 becomes “1”, so that the shift clock (negative clock;Scan Clock) to the F/Fs on the scan paths and the output verifier 7 (andthe pseudo-random pattern generator 2) is suppressed, and the ANDcircuit 55 is brought into the through state by “1” of the control inputpin b1. Whereby, a result (an output of the OR circuit 54) of logicalsum of an output of the F/F 62 and a selection signal from the decoder51 is inputted to the OR circuit 52. At the same time, the result ispassed through the AND circuit 55 and inputted to the F/F 62. As above,“1” is outputted from the decoder 51 to convert an indeterminate value(X value) having been inputted to a specific one of the eight scan pathsto the “1” state value by the OR circuit 52, thereby masking theindeterminate value. When there is simultaneously another indeterminatevalue in an F/F of another scan path, an output (indeterminate value)from that F/F is masked at the next shift clock. Although a portion ofgenerating patterns and a portion of output verification are basicallyindependent, the lower seven bits of the control inputs can be sharedwhen the both circuits are applied in common.

[0095] According to the third embodiment, the output verifier 7 fulfilsfunctions similar to those of the EOR tree circuits 31 and 32 describedabove in the second embodiment. The output verifier 7 compresses aplurality of outputs shifted out from the scan paths #0 through #7 (ORcircuits 52), and outputs them to the outside of the LSI 1C.

[0096] The mask 5 has a function as a control circuit which enables oneof outputs from the scan paths #0 through #7 to be inputted to theoutput verifier 7, and a function as a control circuit which enablesoutputs from scan paths #0 through #7 corresponding to patterns ofpattern numbers in a predetermined range generated by the pseudo-randompattern generator 2 in order to narrow down a pattern number where afault occurs. In order to accomplish the above functions, the mask 5 hasa flip-flop (initialization setting F/F) 57, a logical sum circuit (ORcircuit) 61 and a multiplexer 56 for each scan path, along with a startcounter 58, an end counter 59 and a NAND circuit 60. According to thethird embodiment, the control circuit configured with the elements 57through 61 and the output verifier 7 functioning as the EOR treecircuits together fulfil a function similar to that of the outputselector 30 described above in the second embodiment.

[0097] The initialization setting F/F 57 forms the scan path as anotherF/F 57 forming a scan path, to which “0” or “1” is set by scan-in whenthe test is started. At this time, “0” is set to an F/F for a scan pathto be enabled, whereas “1” is set to F/Fs 57 for the remaining scanpaths.

[0098] The start counter 58 is used to enable outputs corresponding topattern numbers in a predetermined range, together with the end counter59 and the NAND circuit 60. The start counter 58 is set thereto thefirst pattern number in the predetermined range, starts to count thescan clock when the test is started, and switches the output signal from“0” to “1” when the count value becomes the first pattern number, asshown in FIG. 5.

[0099] The end counter 59 is used to enable outputs corresponding topattern numbers in a predetermined range together with the start counter58 and the NAND circuit 60. The end counter 59 is set thereto “the lastpattern number+1” in the predetermined range, starts to count the scanclock when the test is started, and switches the output signal from “1”to “0” when the count value becomes “the last pattern number+1”.

[0100] The NAND circuit 60 outputs a negative AND (negative logicalproduct) of an output signal from the start counter 58 and an outputsignal from the end counter 59. As shown in FIG. 5, while outputscorresponding to pattern numbers in the predetermined range areoutputted from a scan paths, the NAND circuit 60 outputs “0” to enableoutputs from the scan paths. When outputs corresponding to all testpatterns are enabled, for example, “0” is set to the start counter 58and “the maximum value of pattern numbers+1” is set to the end counter59. When only outputs corresponding to one test pattern, for example, anumber of the test pattern is set to the start counter 58 and “thenumber of the test pattern+1” is set to the end counter 59.

[0101] The OR circuit 61 outputs a logical sum of an output signal fromthe initialization setting F/F 57 and an output signal from the NANDcircuit 60. Only when “0” is set to the initialization F/F 57 and theoutput signal from the NAND circuit 60 is “0” (that is, at the time of apattern number in the predetermined range), the OR circuit 61 outputs aresult of logical sum “0” to the F/F 62 through the multiplexer 56 toenable the scan path. The multiplexer 56 selectively switches either anoutput signal from the AND circuit 55 or an output signal from the ORcircuit 61 according to an initialization signal Init, and outputs it tothe F/F 62.

[0102] According to the third embodiment, there is provided a tester(diagnosing means) not shown, as well. An output from the outputverifier 7 is inputted to the tester. Output expected values to beobtained when there is no fault (error) are beforehand stored in thetester, and the tester compares the output expected value with an outputfrom the output verifier 7 to make fault diagnosis.

[0103] According to the third embodiment, when the LSI 1C under testsuch as BIST or the like is diagnosed, scan-in is performed on theinitialization F/F 57 to set “0” to the initialization F/F 57corresponding to a scan path to be enabled with or without concurrentfaults, in the above structure. Whereby, outputs of the scan paths areenabled one by one. The output verifier 7 compresses enabled outputs andsuccessively outputs them to the outside of the LSI IC. The testercompares an output expected value with an output from the outputverifier 7 to make fault diagnosis, and specifies a scan path whoseoutput does not agree with the output expected value as a scan path inwhich a fault exists.

[0104] The above process is repeated plural times (eight times in theLSI IC according to the third embodiment shown in FIG. 4) to diagnoseall the scan paths, whereby all fault positions (scan paths in each ofwhich a fault occurs) can be specified.

[0105] In the first test, “0” is set to the initialization setting F/F57 corresponding to the first scan path connected to the output verifier7 in order to enable only the first scan path, and the test is made onthe first scan path.

[0106] At the start, values of the start counter 58 and the end counter59 are so set as to enable outputs corresponding to all test patterns.When it is known by means of the tester that a fault exists in a scanpath, as a result of the test with all the test pattern, the values ofthe start counter 58 and the end counter 59 are suitably changed toselect a range of pattern numbers where outputs are to be enabled, andthe test is carried out. This process is repeated to narrow down apattern number (a pattern number where a fault occurs) of a test patternrelating to occurrence of the fault, whereby a position of the fault inthe scan path can be specified.

[0107] Similar test is repeated n times (n=8 in the third embodiment) totest up to the n-th scan path connected to the output verifier 7.Whereby, it is possible to not only specify all scan paths in whichfaults exist, but also specify positions of the faults in the scanpaths.

[0108] Like the second embodiment, outputs to be inputted to the outputverifier 7 from a plurality of scan paths are enabled one by one, andthe enabled outputs are compressed by the output verifier 7 andsuccessively outputted to the outside of the LSI 1C in the thirdembodiment. Accordingly, it is possible to accurately specify all scanpaths in which faults exist when fault diagnosis is made on an LSI undertest such as BIST or the like. Even when there are a number ofconcurrent faults because a new manufacturing process is started,accurate, certain fault diagnosis is possible.

[0109] According to the third embodiment, with the start counter 58, theend counter 59, the NAND circuit 60 and the OR circuit 61, outputs fromscan paths corresponding to patterns of pattern numbers in apredetermined range generated by the pseudo-random pattern generator 2are enabled so that fault diagnosis becomes possible. It is therebypossible to narrow down a pattern number where a fault occurs, andspecify a position of the fault in a scan path.

[0110] According to the third embodiment, test patterns generated by thepseudo-random pattern generator 2 are modified by the pattern modifier4, and inputted to plural scan paths, whereby deterministic testpatterns generated by the ATPG can be applied to the LSI 1C within ashort time. In concrete, if the number of inside scan paths is increasedk times, the test time can be shorten to about 1/k. At the same time,the quantity of data of patterns to be stored in the tester can bedecreased. Concretely, if the number of inside scan paths is increased ktimes, the quantity of data can be decreased to about 1/k.

[0111] Although the pseudo-random pattern generator (LFSR or the like) 2used in BIST is utilized, the deterministic pattern adapted inside inthe third embodiment, no sever design rule is put on the designer suchas providing a special control circuit for bus circuit or inserting atest point for improving fault coverage into the circuit. Additionally,a pattern compressor (MISR or the like) used in BIST can be used, and itis possible to prevent the indeterminate state inside the circuit frombeing propagated to the output verifier (MISR) 7 by the mask 5, whichavoids the unverifiable condition.

[0112] According to the third embodiment, test patterns generated by thepseudo-random generator 2 are modified by the pattern modifier 4, andinputted to a plurality of scan paths. It is thereby possible toincrease the number of scan paths to decrease the number of stages ofthe scan paths (the number of F/Fs in each scan path), thus possible tolargely shorten the test time for the LSI 1C. A high-quality test isfeasible without no sever design rule on the designer and without anexpensive tester. Further, an indeterminate value (X value) in outputsfrom a plurality of scan paths formed with F/Fs inside the LSI 1C ismasked by the mask 5, and a result of masked output is verified by theoutput verifier 7. It is thereby possible to prevent a result ofcompression from being ruined by the indeterminate value even if theresult of outputs from the F/Fs are compressed and read out to theoutside.

[0113] [4] Others

[0114] Note that the present invention is not limited to the aboveexamples, but may be modified in various ways without departing from thescope of the invention.

[0115] In the above embodiments, eight scan paths are formed inparallel, and each scan path is formed by serially connecting four F/Fsin each of the LSIs 1A, 1B and 1C. However, this invention is notlimited to this example.

What is claimed is:
 1. A diagnosing apparatus for an integrated circuitcomprising: a pattern generator built in an integrated circuit togenerate test patterns; a plurality of shift registers formed inparallel with sequential circuit elements inside said integratedcircuit, the test patterns generated by said pattern generator beingshifted into said shift registers, respectively; and an outputcompressor for compressing a plurality of outputs shifted out from saidshift registers with check bits of a Hamming code, and outputting thecompressed outputs as a compressed value to the outside of saidintegrated circuit.
 2. The diagnosing apparatus for an integratedcircuit according to claim 1 further comprising: diagnosing means forcomparing an output expected value beforehand obtained with saidcompressed value from said output compressor to make fault diagnosis. 3.The diagnosing apparatus for an integrated circuit according to claim 2,wherein when said diagnosing means diagnoses as a result of thecomparison that a fault occurs at one position, said diagnosing meansspecifies a shift register in which the fault exists.
 4. The diagnosingapparatus for an integrated circuit according to claim 2, wherein whensaid diagnosing means diagnoses as a result of comparison that faultsoccur at two or three positions, said diagnosing means indicatespresence of said faults.
 5. The diagnosing apparatus for an integratedcircuit according to claim 1 further comprising: a pattern modifier formodifying said test patterns generated by said pattern generatoraccording to an external input, then inputting the modified testpatterns to said shift registers.
 6. The diagnosing apparatus for anintegrated circuit according to claim 1 further comprising: a mask formasking an indeterminate value in said outputs from said shiftregisters; and an output verifier for verifying the outputs masked bysaid mask; the outputs of said mask being inputted to said outputcompressor.
 7. A diagnosing apparatus for an integrated circuitcomprising: a pattern generator built in an integrated circuit togenerate test patterns; a plurality of shift registers formed inparallel with sequential circuit elements inside said integratedcircuit, the test patterns generated by said pattern generator beingshifted into said shift registers, respectively; at least one EOR(exclusive OR) tree circuit for compressing a plurality of outputsshifted out from said shift registers, and outputting the compressedoutputs as a compressed value to the outside of said integrated circuit;and a control circuit for enabling one of said plurality of outputs tobe inputted to said EOR tree circuit.
 8. The diagnosing apparatus for anintegrated circuit according to claim 7 further comprising: diagnosingmeans for comparing an output expected value beforehand obtained withsaid compressed value from said FOR tree circuit to make faultdiagnosis.
 9. The diagnosing apparatus for an integrated circuitaccording to claim 8, wherein said control circuit enables saidplurality of outputs one by one; said FOR tree circuit compressesoutputs enabled by said control circuit, and successively outputs thecompressed outputs as said compressed value to the outside of saidintegrated circuit; and said diagnosing means makes said fault diagnosison said shift registers one by one on the basis of said compressed valuefrom said EOR tree circuit to specify a shift register in which thefault exists.
 10. The diagnosing apparatus for an integrated circuitaccording to claim 7, wherein said control circuit enables said outputsfrom said shift registers corresponding to said test patterns of patternnumbers within a predetermined range generated by said pattern generatorto narrow down a pattern number where a fault occurs.
 11. The diagnosingapparatus for an integrated circuit according to claim 7 furthercomprising: a pattern modifier for modifying said test patternsgenerated by said pattern generator according to an external input, theninputting the modified test patterns to said shift registers.
 12. Thediagnosing apparatus for an integrated circuit according to claim 7further comprising: a mask for masking an indeterminate value in saidoutputs from said shift registers; and an output verifier for verifyingthe outputs masked by said mask; said output verifier functioning assaid EOR tree circuit.
 13. A diagnosing method for an integrated circuitcomprising the steps of: generating test patterns by a pattern generatorbuilt in an integrated circuit; shifting the test patterns generated bysaid pattern generator into a plurality of shift registers formed inparallel with sequential circuit elements inside said integratedcircuit; compressing a plurality of outputs shifted out from said pluralshift registers with check bits of a Hamming code, and outputting thecompressed outputs as a compressed value to the outside of saidintegrated circuit; and comparing an output expected value beforehandobtained with said compressed value from said integrated circuit to makefault diagnosis.
 14. The diagnosing method for an integrated circuitaccording to claim 13, further comprising the step of: specifying ashift register in which the fault exists when it is diagnosed as aresult of comparison that a fault occurs at only one position.
 15. Thediagnosing method for an integrated circuit according to claim 13,further comprising the steps of: indicating presence of the faults whenit is diagnosed as a result of comparison that faults occur at two orthree positions.
 16. A diagnosing method for an integrated circuitcomprising the steps of: generating test patterns by a pattern generatorbuilt in an integrated circuit; shifting the test patterns generated bysaid pattern generator into a plurality of shift registers formed inparallel with sequential circuit elements inside said integratedcircuit; enabling a plurality of outputs shifted out from said shiftregisters one by one; compressing the enabled outputs by an EOR(exclusive OR) tree circuit, and successively outputting the compressedoutputs as a compressed value to the outside of said integrated circuit;and comparing an output expected value beforehand obtained with saidcompressed value from said EOR tree circuit to make fault diagnosis. 17.The diagnosing method for an integrated circuit according to claim 16,wherein said fault diagnosis is made on said shift registers one by oneon the basis of said compressed value from said EOR tree circuit tospecify a shift register in which the fault exists.
 18. The diagnosingmethod for an integrated circuit according to claim 16, wherein saidoutputs from said shift registers corresponding to said test patterns ofpattern numbers within a predetermined range generated by said patterngenerator are enabled to narrow down a pattern number where a faultoccurs.
 19. An integrated circuit including sequential circuit elements,built therein being: a pattern generator for generating test patterns; aplurality of shift registers formed in parallel with said sequentialcircuit elements, the test patterns generated by said pattern generatorbeing shifted into said shift registers, respectively; and an outputcompressor for compressing a plurality of outputs shifted out from saidshift registers with check bits of a Hamming code, and outputting thecompressed outputs as a compressed value to the outside of saidintegrated circuit.
 20. The integrated circuit according to claim 19,further built therein being: a pattern modifier for modifying said testpatterns generated by said pattern generator according to an externalinput, then inputting the modified test patterns to said shiftregisters.
 21. The integrated circuit according to claim 19, furtherbuilt therein being: a mask for masking an indeterminate value in saidoutputs from said shift registers; and an output verifier for verifyingthe outputs masked by said mask; the outputs of said mask being inputtedto said output compressor.
 22. An integrated circuit includingsequential circuit elements, built therein being: a pattern generatorfor generating test patterns; a plurality of shift registers formed inparallel with said sequential circuit elements, the test patternsgenerated by said pattern generator being shifted into said shiftregisters, respectively; at least one EOR (exclusive OR) tree circuitfor compressing a plurality of outputs shifted out from said shiftregisters, and outputting the compressed outputs as a compressed valueto the outside of said integrated circuit; and a control circuit forenabling one of said plurality of outputs to be inputted to said EORtree circuit.
 23. The integrated circuit according to claim 22, whereinsaid control circuit enables said outputs from said shift registerscorresponding to said test patterns of pattern numbers within apredetermined range generated by said pattern generator to narrow down apattern number where a fault occurs.
 24. The integrated circuitaccording to claim 22, further built therein being: a pattern modifierfor modifying said test patterns generated by said pattern generatoraccording to an external input, then inputting the modified testpatterns to said shift registers.
 25. The integrated circuit accordingto claim 22, further built therein being: a mask for masking anindeterminate value in said outputs from said shift registers; and anoutput verifier for verifying the outputs masked by said mask; saidoutput verifier fulfilling a function as said EOR tree circuit.